Hidden Inverses: Coherent Error Cancellation at the Circuit Level

TitleHidden Inverses: Coherent Error Cancellation at the Circuit Level
Publication TypeJournal Article
Year of Publication2022
AuthorsB Zhang, S Majumder, PH Leung, S Crain, Y Wang, C Fang, DM Debroy, J Kim, and KR Brown
JournalPhysical Review Applied
Volume17
Issue3
Date Published03/2022
Abstract

Coherent gate errors are a concern in many proposed quantum-computing architectures. Here, we show that certain coherent errors can be reduced by a local optimization that chooses between two forms of the same Hermitian and unitary quantum gate. We refer to this method as hidden inverses, and it relies on constructing the same gate from either one sequence of physical operations or the inverted sequence of inverted operations. We use parity-controlled Z rotations as our model circuit and numerically show the utility of hidden inverses as a function of circuit width n. We experimentally demonstrate the effectiveness for n=2 and n=4 qubits in a trapped-ion quantum computer. We numerically compare the method to other gate-level compilations for reducing coherent errors.

DOI10.1103/PhysRevApplied.17.034074
Short TitlePhysical Review Applied